From a data center down to a single silicon atom.
Rows of server racks fill the room. Overhead trays carry power and network cables to each one.
Illustrative hall, not a floor plan.
A standard 42U cabinet. One rack unit (U) is 44.45 mm tall, and servers come in whole units. Power and network cables run down the back.
600 × 2,000 × 1,200 mm (W × H × D)
Illustrative cabinet.
One GPU server, on rails in the rack. Besides its GPU cards it carries its own CPUs, memory, storage and fans.
4U · up to 8 GPUs
NVIDIA RTX PRO 6000 Blackwell Server Edition
This card has no fan of its own. The server's fans push air through its fin stack.
96 GB GDDR7 with ECC · up to 600 W · PCIe 5.0
Under the shroud and fins sits the package: the silicon die, mounted on a substrate that connects it to the circuit board. GDDR7 memory chips surround it on a 512-bit bus.
NVIDIA GB202
Inside the GPU is a single silicon chip containing 92.2 billion transistors. Its area is split between compute, a large L2 cache and the interfaces to memory.
750 mm² · 128 MB L2 cache · TSMC 4N process
Illustrative floorplan. NVIDIA does not publish one.
The die's compute is grouped into 12 graphics processing clusters, each with 16 streaming multiprocessors (SMs). The RTX PRO 6000 turns on 188 of the 192 SMs.
24,064 CUDA cores · 752 Tensor Cores enabled
Illustrative layout.
Four processing blocks share an RT core and 128 KB of L1 and shared memory. Each block has 32 CUDA cores, a Tensor Core and a 64 KB slice of the register file.
128 CUDA cores · 4 Tensor Cores · 256 KB registers
Illustrative layout.
A Tensor Core multiplies two small matrices and adds a third in one step: D = A × B + C. A 70-billion-parameter model needs about one multiply-add per parameter for every token it writes.
5th generation · adds FP4 and FP6
Illustrative datapath.
Below the wiring, the chip is rows of standard cells between power rails. Each cell is a handful of transistors wired into an adder, a latch or a multiplexer.
Illustrative layout; wiring layers removed.
A FinFET. The gate wraps three sides of a thin silicon fin. Voltage on the gate opens a channel and current flows from source to drain.
Illustrative structure.
The channel is a silicon crystal. Each atom bonds to four neighbours 0.235 nm away.
Lattice constant 0.543 nm